There exist several types of non-idealities that limit the performance of analog circuits. For example, common types of non-idealities include frequency response, noise, nonlinearity, and mismatch. Mismatch is particularly important in the design of high-precision differential circuits, such as differential amplifiers, that include two, ideally symmetric sides. Because of mismatches, the two sides of a differential circuit typically do not exhibit identical properties and bias currents, leading to adverse effects in the performance of these circuits.
In an integrated circuit (IC), mismatches in a differential circuit result from microscopic variations in devices used to implement the differential circuit. For example, random, microscopic variations in the length and width of the gates of two transistors (e.g., MOSFETs) that are identically laid out and used on each side of a differential circuit result in mismatch. In addition, random variances in doping levels in the channels and gates of two identically laid out devices result in threshold (VTH) mismatches.
A traditional approach to reducing the adverse effects of mismatches in a differential circuit is to increase the size of the devices used in its implementation. For example, in a differential circuit that uses MOSFET devices, the width and length of those devices can be increased to reduce their relative mismatches, ΔW/W and ΔL/L. The magnitude of the relative mismatches decreases because as W and L increase, random variations experience greater “averaging.” However, increasing W and L correspondingly results in a higher power requirement and/or a lower speed at which these larger devices can operate.
More specifically, the dynamic power of a MOSFET device is generally given by the following equation:Pdynamic=CVDD2fwhere C is the channel capacitance (which is proportional to WL), VDD is the supply voltage, and f is the switching frequency or average switching frequency of the MOSFET. As can be readily seen, any increase in W or L leads to an increase in the channel capacitance C and a corresponding increase in the dynamic power consumption of the MOSFET. To compensate for the additional power requirement, the frequency or speed at which the device operates can be reduced or additional power can be supplied. Either way, there is a tradeoff between increasing the size of the device to limit the magnitude of relative mismatches and the power and/or speed at which the device operates.
Therefore, what is needed is a system for minimizing the adverse effects caused by mismatches used in the implementation of differential circuits, while at the same time limiting additional power requirements and/or speed limitations.
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.